1. Field of the Invention
The present invention relates to a spiral RF inductor. In particular, the present invention relates to a spiral RF inductor on low k substrate formed on a silicon wafer to give low k, low loss and high Q value.
2. Description of the Related Art
Microwave inductor is always produced by forming a spiral on a ceramic substrate of aluminum oxide content (˜96%),or a glass (silicon dioxide) substrate with k value of 7.8 and 3.9, respectively with screen printing technique. These substrates can not use the existing silicon process micro fabrication equipments. FIG. 1 is a cross sectional structure of a conventional spiral chip inductor of the prior art. An alumina ceramic substrate 102 is a square type substrate. By using screen printing, a Ti or Ni
Pattern of the first layer of the spiral is formed on the surface. Then a first layer of the spiral 106 is formed by copper plating. A layer of silicon dioxide or USG (un-doped silicon glass) is deposited on the substrate 102 to form an insulating layer 104. Next, a via-106 hole 108 is opened and a copper layer is formed by plating. Last, by lithography, form the crossover copper and a second layer of the spiral pattern.
This process makes use of screen printing or contact aligner to form the pattern of Ti, Ni or copper. The equipment is not accurate enough, so that the value of inductance will be changed from wafer to wafer, even chip to chip. Thus the frequency response can be affect by the spiral inductor.
The other disadvantage of the prior art is that the dielectric under the first and second layer of the spiral are alumina and silicon dioxide, respectively, which have higher dielectric constant of 7.8 and 3.9, the quality factor (Q) of the spiral is low.
Another disadvantage of the prior art is that the ceramic or glass substrate is very hard and can not be thinned by lapping, so that it is not suitable for handy device such as cellular phone, which has thinner spiral inductors.
In the U.S. Pat. No. 6,153,489 to Min Park et al., a trench-shaped silicon porous 19 is formed under the inductor, the parasitic capacitance between metal lines 16 and the silicon substrate 10 is decreased. However, the second dielectric layer 14 between the metal lines 16 and the first metal level 13 is still high. In the U.S. Pat. No. 6,287,936 to Ernesto Perea et al., using electroplating to form a porous silicon on the rear face FAR to a thickness of H2. Although the porous silicon is very thick, the thickness of h2 is very hard to control and the dielectric between the metal spiral ML and the first metal level is also still high.
There is a need for fabricating a spiral inductor with higher quality factor and can be thinned by lapping, thus smaller and finer chip inductors can be produced.